1. Field of the Invention
This invention relates to a reverse voltage generation circuit that generates a voltage of the opposite polarity to an input voltage.
2. Description of the Related Art
The reverse voltage generation circuit is used as a power supply to an LCD (Liquid Crystal Display) driver circuit that provides an active matrix type LCD panel with gate signals, for example. The reverse voltage generation circuit generates a negative voltage (−15V) from a positive voltage (+15V), for example.
FIG. 5 is a circuit diagram of a reverse voltage generation circuit according to prior art. The reverse voltage generation circuit is composed of a first and a second charge transfer MOS transistors TR21 and TR22 of an N-channel type, a first and a second level shift circuits LS21 and LS22 which control turning on and off of the first and the second charge transfer MOS transistors TR21 and TR22 respectively, a capacitor 10 (usually a capacitor externally connected to an integrated circuit) and a driver circuit 11 that is a CMOS inverter made of a first driver MOS transistor TR23 of a P-channel type and a second driver MOS transistor TR24 of the N-channel type.
The first and the second charge transfer transistors TR21 and TR22 are simply referred to as TR21 and TR22 in the following explanation, as well as referring to the first and the second driver MOS transistors TR23 and TR24 simply as TR23 and TR24.
An example operation of the circuit will be described hereafter. An input signal S23 to a gate of TR23 and an input signal S24 to a gate of TR24 are turned to a low level (Vss) to turn TR23 on and turn TR24 off, after TR22 is turned off by the second level shift circuit LS22. Then TR21 is turned on by the first level shift circuit LS21. As a result, a node N23 that is an output node of the driver circuit 11 is set to a voltage VH, while a node N21 that is a point of connection between TR21 and TR22 is pulled to a ground voltage (reference voltage) Vss.
Next, after turning TR21 off, the input signal S23 to the gate of TR23 and the input signal S24 to the gate of TR24 are turned to a high level (VH) to turn TR23 off and turn TR24 on. After that, when TR22 is turned on, a voltage at the node N21 is lowered due to a capacitive coupling through the capacitor 10, a current flows from the node N22 to the node N21 through TR22 and a voltage at the node N22 and a voltage at an output terminal 20 connected to the node N22 are lowered.
Next, after turning TR22 off, the input signal S23 to the gate of TR23 and the input signal S24 to the gate of TR24 are turned to the low level (Vss) to turn TR23 on and turn TR24 off. Then TR21 is turned on by the first level shift circuit LS21 to return to the initial state. Repeating the operation described above brings the node N22 to −VH that is a reverse polarity voltage of the voltage VH. Therefore, the negative voltage −VH is generated from the positive voltage VH with this reverse voltage generation circuit.
The input signals S21 and S22 to the first and the second level shift circuits LS21 and LS22 are determined based on a voltage-logic assuming the voltage VH as the high level and the ground voltage Vss as the low level. The first and the second level shift circuits LS21 and LS22 convert the input signals swinging between the voltage VH and the ground voltage Vss to signals swinging between the voltage VH and a voltage at the node N22, in order that TR21 and TR22 are completely turned off. When the reverse voltage generation circuit reaches a stationary state after repeating the operation described above, the voltage at the node N21 swings between the ground voltage Vss and −VH and the voltage at the node N22 becomes −VH.
The reverse voltage generation circuit described above has been manufactured by a CMOS process using an N-type semiconductor substrate. Relevant descriptions on the technologies mentioned above are provided, for example, Japanese Patent Publication No. 2001-258241.
A lowest voltage provided to an LSI (Large Scale Integration) is applied to a substrate of N-channel MOS transistors in an ordinary LSI in order to reverse-bias P-N junctions. In a reverse voltage generation circuit LSI that generates a negative voltage from a positive voltage, however, a substrate of an N-channel MOS transistor connected to the generated voltage needs to be connected to the generated voltage or a voltage lower than the generated voltage, since the reverse voltage generation circuit generates the voltage lower than the voltage provided to the LSI.
And if the substrate voltage of all N-channel MOS transistors in the reverse voltage generation circuit is unified to the generated voltage, driving capacity of an N-channel transistor having a source connected to the ground voltage Vss (TR21 and TR24, for example) is reduced since a back-gate bias is applied to the N-channel MOS transistor. Therefore, the N-channel MOS transistors are separated from each other with individual P-wells.
Increasing need in recent years for integrating the reverse voltage generation circuit into an LSI as a power supply requires integrating the reverse voltage generation circuit not only into an LSI using an N-type semiconductor substrate but also into an LSI using a P-type semiconductor substrate.
However, when the reverse voltage generation circuit of FIG. 5 is formed in the P-type semiconductor substrate, there arises a problem described below. The N-channel MOS transistors TR21, TR22 and TR24 are formed in the P-type semiconductor substrate. And the substrate voltage of these transistors is made to be the output voltage of the reverse voltage generation circuit (the output voltage of TR22). However, the output voltage is not yet generated at the time the power supply is turned on (at the beginning of the operation of the circuit). As a result, the substrate voltage of the transistors is unstable when the power supply is turned on. If the substrate voltage is somewhat higher than the ground voltage Vss, the transistor with its source connected to the ground voltage Vss is back-gate biased with a reverse voltage, leading to a reduction in a threshold voltage and possibly to causing a leakage current in the transistor.